Bandgap voltage reference circuits are well known in the art from the early 1970's as is evidenced by the IEEE publications of Robert Widlar ( IEEE Journal of Solid State Circuits Vol. SC-6 No 1 February 1971) and A. Paul Brokaw (IEEE Journal of Solid State Circuits Vol. SC-9 No 6 December 1974).
These circuits implement configurations for the realization of a stabilized bandgap voltage. As discussed in David A. Johns and Ken Martin “Analog Integrated Circuit Design”, John Wiley. & Sons, 1997, incorporated herein by way of reference, these circuits and other modifications to same are based on combining the voltage of a forward based diode (or base emitter junction) having a negative temperature coefficient from a voltage proportional to absolute temperature (PTAT). Typically, the PTAT voltage is formed by amplifying the voltage difference (ΔVbe) of two forward biased junctions operating at different current densities.
The formation of a voltage reference circuit is typically provided by the addition of this PTAT voltage which increases with absolute temperature to a voltage that substantially decreases with absolute temperature, i.e. a CTAT (complementary to absolute temperature) voltage. Similarly, a substantially constant reference current source is typically generated by the addition of a PTAT and CTAT current. The PTAT and CTAT currents may be generated by mirroring PTAT and CTAT voltages across resistors. The reference current or voltage source may provide a constant current or voltage over a temperature range of interest, or a current or voltage with a fixed chosen temperature dependency.
FIG. 1 shows an exemplary circuit diagram for generating a current reference source according to the prior art. It consists of two operational amplifiers, A1 and A2, two diode connected transistors Q1 and Q2, three resistors, R1, R2 and R3 and six PMOS transistors, M1, M2, M3, M4, M5 and M6. The sources of M1, M2, M3, M4, M5 and M6 are connected to VDD. The inverting input of the operational amplifier A1 is connected to the inverting input of the operational amplifier A2, the emitter of the transistor Q1 and to the drain of the PMOS M1. The non-inverting input of the operational amplifier A1 is connected to emitter of transistor Q2 via a resistor R1 and to the drain of the PMOS M3. The output of the operational amplifier A1 is connected to the gate and drain of M2 and the gates of M1, M3 and M5. The non-inverting input of the operational amplifier A2 is connected via a resistor R2 to ground and to the drain of M4. The output of the operational amplifier A2 is connected to the gates of M4 and M6. The drain of M6 is connected to the drain of M5. The drain of M6 is also connected to ground via a resistor R3. It will be appreciated from the circuit of FIG. 1 that the operation of the op-amp A1 is such as to keep the voltage at its terminals, points “a” and “b”, substantially at the same voltage level. This forces currents into the emitter of Q1 and Q2 flowing from the PMOS mirror devices M1 and M3.
Q2 is chosen to have an emitter area “n” times larger than Q1, and as such the two diodes are operating at different current densities and a PTAT voltage, ΔVbe, is generated across resistor R1. This is equal to the base-emitter voltage difference between Q1 and Q2. As the voltage across R1 is a PTAT voltage, the current flowing through R1, M1, M2, M3 and M5 is a PTAT current. However the voltage at node “a” and therefore the voltage of the inverting terminal of A2 is a CTAT voltage, as it is the base-emitter voltage of transistor Q1. As both terminals of the operational amplifier A2 are forced to be at the same voltage level, the voltage of the non-inverting input of A2 is also a CTAT voltage and is produced across R2. Therefore, the drain current of M4 is a CTAT current, which in turn results in the drain current of M6 being a CTAT current As the current flowing through R3 is the sum of the currents flowing through the drains of M5 and M6, it will be appreciated that the resulting reference current flowing through R3 will be a combination of PTAT and CTAT currents, while the reference voltage across R3 will be a combination of PTAT and CTAT voltages. The reference levels shown are typically ground potentials.
One of the problems associated with this prior art circuit is that it requires two amplifiers and multiple current mirrors to generate the PTAT and CTAT currents which are required for operation of the circuit in the necessary fashion.
An alternative implementation of a current and voltage reference source that attempts to overcome this problem is shown in FIG. 2, which requires only one amplifier for operation. The same reference numerals are used for the same components. It will be appreciated that this circuit is similar in operation to the circuit of FIG. 1. However, the circuit differs in that the connection between the inverting input of the operational amplifier A1 and the operational amplifier A2 in FIG. 1 is replaced with a direct connection between the inverting terminal of A1 to ground via a resistor R2a. The connection between the output of A1 and M2 and M5 of FIG. 1 is also no longer present in FIG. 2.
Additionally, the non-inverting terminal of operational amplifier A1 is connected in FIG. 2 to ground via a resistor R2b. If the resistors R2a and R2b were not included, the PTAT current through M1, M3 and M6 would be identical to that of FIG. 1. However, by including R2a and R2b, the voltage drop over R2a and R2b is the same CTAT voltage. Therefore, it will be appreciated that the drain current of M1, M3 and M6 will now be a combination of PTAT and CTAT currents. This, it will be appreciated, also produces a reference voltage and current source as required.
However, the embodiment of FIG. 2, while an improvement over FIG. 1, suffers in that a relatively large area of silicon is required to implement the circuit and/or there is a high level of power consumption, due to the two resistors having direct paths from the amplifier inputs to the ground. In common embodiments of the prior art, higher value resistors are used to save power. However this in turn results in a larger area, which therefore increases the manufacturing costs. It will be appreciated therefore that in the embodiments of the prior art designs area is conventionally traded off against power consumption.
There is therefore a need to provide an improved reference current and reference voltage generating circuit.